1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a package is configured by loading a semiconductor chip on a package substrate.
2. Description of the Prior Art
As a kind of a package for a semiconductor device, there has been known one with a structure in which a semiconductor chip and the package substrate are united mechanically as well as electrically by loading a semiconductor chip having solder bumps with its face down on the package substrate. Moreover, in the semiconductor device of this kind, a constitution of a semiconductor device, the so-called flip-chip ball grid array (FCBGA) package, in which balls of a BGA are disposed in advance on the back face of the package substrate and a semiconductor package is mounted on a mother board with respect to the BGA balls.
FIG. 10 shows an example of the FCBGA package, in which a package substrate 101 is obtained by forming a multilayer conductive layer, not shown, on an insulating substrate, rectangular frame-like Cu reinforcing plates 108 are bonded to the periphery of the top face of the packaging substrate 101 by means of an adhesive resin 109, a semiconductor chip 105 having solder bumps 106 is loaded with its face down on the surface of the package substrate 101 within the region surrounded by the reinforcing plates 108, and the solder bumps 106 are soldered to loading pads 104 of the package substrate 101. Underfill resin 107 is filled in the gap between the semiconductor chip 105 and the package substrate 101 covering the solder bumps to reinforce the bonding strength of the junction. An epoxy resin with Young""s modulus 900 kgf/mm2 and coefficient of thermal expansion 30 ppm/xc2x0 C. is used as the underfill resin 107, and the underfill 107 is cured by heating it at 150xc2x0 C. for about 1 hour. Silver paste 110 is applied to the top face of the semiconductor chip 105, an adhesive resin 111 is applied to the top face of the reinforcing plates 108, a Cu lid 112 is arranged covering the paste and the resin, and the lid 112 is settled there by curing the adhesive resin 111. Then, an FCBGA package is formed by arranging the BGA balls 114 to respective ball pads 113 disposed on the bottom face of the package substrate 101.
In the semiconductor device of this kind, the semiconductor chip 105 and the package substrate 101 are often formed using silicon and resin, respectively. Because of this, when the semiconductor device is subjected to a thermal history, thermal stresses are generated between the semiconductor device 105 and the package substrate 101 due to the difference in the coefficient of thermal expansion between silicon and the resin of the package substrate (the coefficient of thermal expansion of silicon being 3 ppm/xc2x0 C., and the coefficient of thermal expansion of the package substrate being 16 to 18 ppm/xc2x0 C.), there is a possibility of generating a fracture in the junction of the semiconductor device 105 and the package substrate 101, namely, in the bonded parts of the solder bumps 106. Even though the possibility does not advance so far as to a fracture, there may occur a case in which a bending force is applied to the semiconductor device 105 and the package substrate 101 which may cause a warp in the semiconductor device 105, and further in the package substrate 101, as shown in FIG. 11. In particular, in the semiconductor device of the kind in recent years, the package substrate 101 is formed so thin that warping tends to be generated in the package substrate at directly below the semiconductor device 105. When such a warp is generated, the coplanarity of the BGA balls 114 in this region is degraded, which results in a state in which a part of the BGA balls 114 fails to make contact with the circuit pattern on the surface of the mother board M indicated by an imaginary line in the figure, resulting in a problem of deterioration in the reliability of the mounting. Moreover, if mounting is forced in such a condition, an excessive force is applied to the package board 101 and the semiconductor chip 105, leading to such problems as the generation of cracks or breakage in the semiconductor chip 105, and further, breaking of the solder bum junction parts during a heat cycle test.
As a first prior art technology for solving problems caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the package substrate connected in the so-called flip-chip form, there has been proposed a technology as disclosed in Japanese Patent Applications Laid Open, No. Hei 11-145336. This is a technology in which the coefficient of thermal expansion of the underfill resin is chosen to be larger than the coefficient of thermal expansion of the semiconductor chip and smaller than that of the package substrate, that is, to have an intermediate value between the coefficients of thermal expansion of the semiconductor chip and the package substrate. With this arrangement, it is possible to relax thermal stresses, in particular the shearing force generated by a heat cycle in the junction between the semiconductor chip and the package substrate, by means of the underfill resin, and is possible to prevent fracture at the junction of the semiconductor chip. In the first prior art technology, since an epoxy resin is used as the underfill resin, the semiconductor chip and the package substrate are held in a united state when the underfill resin is cured, it is possible to relax the shearing force in the junction. However, it is difficult to prevent bending deformation, namely, warp of the semiconductor chip and the package substrate that is caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the package substrate. Furthermore, the first prior art technology is for an example of the package substrate made of a ceramic, and it is not clear whether or not it is also applicable to a package substrate made of a resin.
In a second prior art technology disclosed in Japanese Patent Applications Laid Open, No. 2000-40776, there is proposed a technology in which the solder bumps of the semiconductor chip are covered with a high elasticity resin, and a low elasticity resin is filled in between the semiconductor chip and the package substrate so as to cover the solder bumps and the high elasticity resin. According to this technology it is possible for the high elasticity resin to prevent the fracture of the solder bumps by relaxing the stress (shearing force) exerted on the solder bumps by reducing the relative displacement between the semiconductor chip and the package substrate accompanying the difference in the coefficient of thermal expansion. At the same time, the low elasticity resin can prevent the peeling of the low elasticity resin by absorbing and dispersing the stress generated between the semiconductor chip and the package substrate.
However, it became clear as a result of experiment by the present inventor, as will be described later, that the effect of preventing warping that is generated in the semiconductor chip and the package substrate by relaxing the stresses generated between the semiconductor chip and the package substrate cannot be expected by the use of a silicone resin with Young""s modulus of less than 200 kgf/mm2 as is employed as the low elasticity resin in the second prior art technology. In other words, although a certain degree of warp prevention effect can be obtained by the use of a low elasticity resin having the Young""s modulus in the neighborhood of the value mentioned above, for semiconductor devices with a chip size of a square with a side of 5 to 10 mm (called a 5 to 10 mm square), in the recent semiconductor devices which adopt a large chip size of 15 mm square or so, it is difficult, since the warpage increases following the chip size, to prevent the warpage in large-sized semiconductor chips. Here, it is conceivable to further lower the Young""s modulus of the low elasticity resin, but it is difficult to reduce the Young""s modulus of the silicone resin described in the report to below 100 kgf/mm2, and eventually it is difficult to prevent the warp in the semiconductor chip or in the package substrate of semiconductor devices of large chip size and the fracture of solder bumps due to heat cycle test.
Furthermore, there is a third prior art technology disclosed in Japanese Patent Applications Laid Open, No. 2001-127095. This is a semiconductor device in which a layer insulating film and a resin sealing layer are formed on an electrode pad formation face of the semiconductor chip, and bump electrodes are formed as external connection terminals which penetrate the layer insulating film and the resin sealing layer to be exposed to the outside. The technology described in the report is such that in order to prevent generation of cracks in the bump electrodes accompanying thermal stress caused due to the difference in the coefficient of thermal expansion between the package substrate that loads the semiconductor chip and the bump electrodes, a part of the layer insulating film is formed of a resin with a specified low coefficient of thermal expansion and a specified low elastic modulus. According to this technology, it is possible to prevent cracks in the bump electrodes by relaxing thermal stress in the layer insulating film, and to enhance the connection reliability after packaging.
However, in the third prior art technology, it is necessary to form a semiconductor chip through flip-chip connection by forming the bump electrodes after providing the layer insulating film and the resin sealing layer, so that the number of manufacturing steps is increased which becomes an obstacle to the reduction in the cost. Moreover, since this prior art technology is not for semiconductor devices in which an underfill resin is filled in the gap between the semiconductor chip and the package substrate, it is difficult to apply it to such a semiconductor device in which an underfill resin is filled in the space between the semiconductor chip and the package substrate and tries to eliminate the problems described in the above through improvent of the underfill resin, as in the present invention.
It is the object of the present invention to provide a semiconductor device which can prevent the warp in the semiconductor chip and the fracture of solder bumps in heat cycle test in a semiconductor device with large chip size and realize simplification of the structure and reduction in the cost as well. It is to be noted that xe2x80x9cprevention of warpxe2x80x9d mentioned in the foregoing and in the following includes suppression of the warpage within an allowable warpage range.
According to this invention, in a semiconductor device formed by connecting electrodes of a package substrate composed of a resin to electrodes of a semiconductor chip formed of a semiconductor of silicon, an underfill resin having the Young""s modulus less than 100 kgf/mm2 is filled in the gap of the junction of the semiconductor chip and the package substrate.